RESIST Resilience against Silent Silicon Threats

Abstract. Hyperscalar reports of silent data corruptions (SDCs)—presumed to be caused by silicon manufacturing defects—have motivated the development of functional tests for detecting defective CPUs and their use in hyperscalar fleet studies. Interestingly, all such tests seem to assume that defects induce consistent errors: two instances of the same instruction within the same thread, given the same architectural inputs, always produce the same wrong architectural output. We find that this assumption unnecessarily restricts which programs can serve as tests—biasing which defect-induced errors are triggered and detected—and limits identification of affected instructions to those impacted by errors that short, targeted tests can reproduce—biasing how errors are characterized.

This talk will present ITHICA, which automatically generates functional tests for defect-induced errors from arbitrary programs by inserting intra-thread, instruction-level error checks, primarily leveraging instruction duplication and output comparison. Our key insight, challenging the assumption above, is that the most pernicious defects—those most likely to escape manufacturing testing—cause inconsistent errors: two executions of the same instruction, given the same inputs, can produce different architectural outputs depending on the execution context in which they run. By exploiting this insight, ITHICA enables arbitrary programs to serve as tests and localizes affected instructions upon error detections, overcoming both aforementioned limitations of prior functional tests. We use ITHICA to transform industrial hyperscalar test programs (our baseline), datacenter workloads, and common libraries into functional tests, and evaluate them on over 3,000 CPU servers. ITHICA error checks detect 39% more defective servers than native checks within the ITHICA tests derived from our baseline programs, and enable novel findings on defect behavior that challenge conclusions drawn by prior hyperscalar fleet studies.

Bio. Caroline Trippel is an Assistant Professor in the Computer Science and Electrical Engineering Departments at Stanford University, where she leads the High Assurance Computer Architectures Lab. A central theme of her work is leveraging formal methods, especially automated reasoning, techniques to design and verify hardware systems. Trippel's research has been recognized with IEEE Top Picks and Best Paper Award distinctions, a Sloan Research Fellowship, an NSF CAREER Award, the Intel Rising Star Faculty Award, the 2020 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award, and the 2020 CGS/ProQuest® Distinguished Dissertation Award in Mathematics, Physical Sciences, & Engineering.

Abstract. In this talk we present the state-of-the-art in microarchitectural modeling and simulation-based methods to demystify the problem of silicon defects in modern CPU and AIA (AI accelerators) chips. Microarchitectural simulation is harnessed for the development of effective functional programs for defect detection (and thus catching them before they lead to user programs' silent corruptions) as well as for measuring the probabilities and rates of silent and loud data corruptions in modern architectures (and thus assisting efficient fault tolerance design techniques across the abstraction layers).

Bios. Nikos Karystinos is a Ph.D. student and a member of the Computer Architecture Lab at the Department of Informatics and Telecommunications of the University of Athens. His research interests include microarchitectural simulation, hardware reliability, and program generation. Karystinos received his BSc and MSc degrees in computer science (with a specialization in computer systems: software and hardware) from the University of Athens.

Odysseas Chatzopoulos is a Ph.D. student and a member of the Computer Architecture Lab at the Department of Informatics and Telecommunications of the University of Athens. His research interests include reliability analysis of heterogeneous system architectures from edge devices to hyperscale systems. Chatzopoulos received his BSc degree in computer science from the University of Athens.

Dimitris Gizopoulos is a professor at the Department of Informatics and Telecommunications of the University of Athens, Greece, and director of the Computer Architecture Lab. His team's research interests include the complex interactions among performance, power, and reliability of computing systems built on CPUs, GPUs, and AI accelerators. He serves as associate editor and guest editor for several IEEE and ACM publications (including IEEE CAL, ACM CSUR, and IEEE TC) and is a member of the steering, organizing, and program committees of international computer architecture, hardware, and systems conferences. He is a Fellow of IEEE, an ACM Distinguished Member, and a Golden Core member of the IEEE Computer Society. He is the General Chair of the IEEE/ACM MICRO 2026 symposium.